Probabilistic Modeling and Optimization for Circuit Reliability

Probabilistic Modeling and Optimization for Circuit Reliability

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Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the increase in transistor integration capacity to implement complex systems also leads to the increase in process variations. Despite these difficulties, it is expected that systems remain reliable while delivering the required performance. Reliability and variability are emerging as a new design challenge, thus pointing to the importance of modeling and analysis of transient faults and variation sources for the purpose of guiding the design process.TARGET CIRCUIT: netlist, layout information and input vector probability distributions HSPICE: gate chain simulations MATLAB: response surface ... Block diagram of the proposed approach. show the error of linear RSM method for output glitch duration. ... on average less than 1% and 4% for NAND, NOR, and XNOR, with larger errors for the INV (inverter), and XOR gate (8% and 10%, respectively).

Title:Probabilistic Modeling and Optimization for Circuit Reliability
Author: Natasa Miskov-Zivanov
Publisher:ProQuest - 2008

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